As designers and manufacturers continue to shrink the size of circuit components, the shapes reproduced on the substrate through photolithography become smaller and are placed closer together. This reduction in feature size and spacing increases the difficulty of faithfully reproducing the image intended by the design layout onto the substrate and can create flaws in the manufactured device. To address the problem, one or more resolution enhancement techniques are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process.
One of resolution enhancement techniques, “optical proximity correction” or “optical process correction” (OPC), attempts to compensate for light diffraction effects. When light illuminates the photomask, the transmitted light diffracts, with light from regions with higher special frequencies diffracting at higher angles. The resolution limits of the lens in a photolithographic system make the lens act effectively as a low-pass filter for the various spatial frequencies in the two-dimensional layout. This can lead to optical proximity effects such as a pull-back of line-ends from their desired position, corner rounding, and a bias between isolated and dense structures. The optical proximity correction adjusts the amplitude of the light transmitted through a lithographic mask by modifying the layout design data employed to create the photomask. For example, edges in the layout design may be adjusted to make certain portions of the geometric elements larger or smaller, in accordance with how much additional light exposure (or lack of exposure) is desired at certain points on the substrate. When these adjustments are appropriately calibrated, overall pattern fidelity (printed vs. targeted) is greatly improved, thereby reducing optical proximity effects.
In addition to the edge adjustment, sub-resolution assist features (SRAF) are often inserted to address the iso-dense bias problem. Sub-resolution assist features, sometimes also known as “scattering bars,” are themselves too small to be resolved by the imaging system. When they are inserted into the layout, sub-resolution assist features can, however, provide a dense-like environment for isolated features. As such, isolated features will print more like dense features.
One challenge for applying the resolution enhancement techniques is computation time and costs. For a design having hundreds of millions of or even billions of gates, an optical proximity correction and sub-resolution assist features insertion process can require thousands of processors to operate for multiple days. Any technique that can speed up the process and/or require less computing resources is highly desirable.
Another challenge is consistency. Numerical noise caused by computation involved can lead to different corrections for the same layout pattern in different locations. While the deviations are usually small, it is desirable for a resolution enhancement tool to produce a consistent result for the same layout patterns. This is particularly true for designs with repetitive patterns such as memory cells.